1. Field of the Invention
The present invention relates to a reset circuit, and particularly relates to a reset circuit which outputs a power-on reset signal and a power-down reset signal.
2. Description of the Related Art
A power-on reset circuit generates a power-on reset signal to perform a reset during power-on. A power-down reset circuit generates a power-down reset signal to perform a reset during power-down. If the power-on reset circuit and the power-down reset circuit are formed by separate circuits, the circuit area thereof becomes larger. Moreover, it is difficult to control the timing when the power-down reset signal occurs during power-down.
Further, a power-on reset circuit having a hysteresis characteristic is disclosed in the following Patent Document 1.
(Patent Document 1)
Japanese Patent Application Laid-open No. Hei 5-183416